LTE-S Hardware Plattform

Combined DSP/FPGA platform for development of next generation radio interfaces like 3G LTE.

Combined DSP/FPGA platform for development of next generation radio interfaces like 3G LTE. The combination of high performance FPGA and multicore communications infrastructure DSP offers a high flexibility signal processing performance. The platform has been designed for implementation of 3G LTE downlink and uplink layer 1 and layer 2 processing. It is well suited for all applications which require high bandwidth real-time processing.

The block diagram shows the general architecture of the LTE-S board. The key components are three Xilinx FPGAs and two Texas Instruments DSP.

The XC5VFX100T FPGA covers the following functions:

  • board control and configuration
  • HOST interface
  • internal Power PC 440 with embedded Linux operating system

The XC5VSX240T and XC5VSX95T FPGA and the two TMS320TC6488 DSPs offer resources for hard- and software design. Additionally two add-on slots are placed on board to extend the hardware resources by additional modules. The data communication between FPGA is realised via parallel busses and serial high speed interfaces. The communication between the DSPs and between DSP and FPGA is done via the Serial RapidIO Interface.


  • Hardware platform for high bandwidth real-time signal processing
  • Base station development
  • Test terminal development
  • 3G LTE physical layer decoding
  • 3G LTE MAC layer decoding
  • 3G LTE higher layer implementation

The LTE-S board has the following key features:

  • 2 user-programmable FPGAs (1 XC5VSX240T and 1 XC5VSX95T)
  • 2 Faraday DSP TMS320TCI6488 in Serial RapidIO chain
  • CPRI interface for RF frontend connection
  • Gigabit Ethernet interface for core network connection
  • Gigabit Ethernet interface using Broadcom switch to the 2 FPGAs and 2 DSPs
  • direct Gigabit Ethernet interface to XC5VSX240T
  • 4 GB DDRII RAM connected to XC5VSX240T in 2 DIMM modules
  • 256 MB DDRII RAM for each DSP
  • 2 SFP serial gigabit connections to XC5VSX240T for e.g. CPRI
  • 2 optional SFP connections to DSP antenna interface for CPRI
  • optional USB 2.0
  • 2 JTAG chains for FPGA and DSP
  • onboard PLL for global clock generation
  • additional PLL for CPRI clock regeneration
  • MMC card interface for configuration data of FPGA and DSP
  • XC5VFX100T as board controller using embedded Linux
  • 2 firmware EEPROMs for save update over Ethernet
  • several parallel connections between all 3 FPGAs
  • 2 bidirectional GTP lanes between all 3 FPGAs
  • 2 extension slots for several add-on modules (compatible with FFP Basic+ format)
  • single 5V power supply