In numerous projects, we are increasingly using very fast A/D and D/A converters with sampling rates > 1 GSPS. These devices often have serial interfaces pursuant to the JESD204B standard. Compared to conventional parallel LVDS interfaces, this procedure offers the advantage that significantly fewer impedance-controlled and equal-length cable connections are required. For the required serial connections between FPGA and converter, the high-speed transceivers can be used.
The implementation of the JESD204B functionality can be performed entirely in the FPGA and does not require any additional electronic components.
The exact clock and time synchronisation of a large quantity of converters, as present in Massive MIMO systems, can be realised with the JESD204B interface.